1. Field of the Invention
The present invention generally relates to the general problem of limiting the power consumed by memory array sense amplifiers. More particularly, this invention presents a circuit and a method for providing a high speed and low power sense amplifier. More particularly, this invention provides a circuit and a method which automatically limits the precharge time and voltage, which limits the power consumed and speeds the voltage transitions.
2. Description of the Prior Art
A typical dynamic random access memory, DRAM, contains several subsystem circuits which make up the whole memory system. For example, there is the address decode subsystem which takes the memory address bus as input and outputs word lines which select groups of memory cells for writing and reading. In addition, there are input data drivers which interface with the memory array data bit lines for purposes of writing new data into the memory cells. Then, there are the memory arrays themselves which are made up of memory cells. For purposes of reading previously stored data out of the memory cells, there is a sense amplifier subsystem. This subsystem senses the data level of bit lines in order to report or read the value of memory cells. The sense amplifier circuitry interfaces with bits lines which are attached to the memory cells and with data output drivers which are the output lines of the memory system. In the prior art, the power dissipation and speed of sense amplifiers are important design issues, since any improvement to power consumed by sense amplifies and in the speed of sense amplifiers are magnified several times due to the wide-spread use of dynamic random access memory, DRAM.
U.S. Pat. No. 6,363,023 (Anderson, et al.) “Bi-directional Differential Low Power Sense Amp and Memory System” describes a device and a method which reduces power consumption in memory devices. It describes a bi-directional circuit which can be used for both read and write operations.
U.S. Pat. No. 6,301,179 (Lawson) “Self-equalized Low Power Precharge Sense Amp for High Speed SRAMs” discloses memory sense amplifier subsystem which uses complementary PMOS FETs and NMOS FETs.
U.S. Pat. No. 6,249,470 (Anderson, et al.) “Bi-directional Differential Low Power Sense Amp and Memory System” discloses a sense amplifier subsystem which utilizes differential data buses which further reduces power consumption while providing high performance.